A processor in a computer system typically carries out the execution of instructions in a series of stages, which may be referred to as a pipeline. Each of these stages may be performed by a different section of the processor. As an example, an instruction may be decoded by a decoder and, at a later time, the decoded instruction(s) executed by a functional unit. In an “out-of-order” architecture, instructions may be executed by an execution unit in a different order than is specified by the program from which they are derived. In such a case, the instructions may be dispatched by a dispatcher into a scheduler, and the scheduler may determine the order in which the instructions are issued to a functional unit that executes the instructions.
The instructions that a processor performs typically use registers to store data. An instruction may have one or more source operands, which may be stored in register(s), and an instruction may produce a result, which may also be stored in a register. An instruction may be said to use a register if a source operand is stored in that register (i.e., it reads from the register) or a result is stored in that register (i.e., it writes to the register). For example, for a given instruction the processor may read a data operand out of register R0, read a data operand out of register R3, add these data operands, and then store the results back into register R4. Some prior architectures may have a register cache, and in such architectures source operands may be obtained from the register cache or, if a cache miss, from the register file unit. In prior architectures, every instruction in the pipeline must flow through the register file unit (or associated register cache). For example, some prior out-of-order architectures have the register file unit either in the main pipeline after the schedulers, in which case the register file unit may be accessed as instructions are scheduled out of the scheduler to functional units, or may have the register file unit in the main pipeline before the schedulers, in which case the register file unit may be accessed as instructions enter the scheduler.